The Electronic Design Automation Consortium (EDAC) has chosen electronic design automation pioneer Yen-Son (Paul) Huang as the 2000 recipient of its Phil Kaufman Award. Huang, who serves as chairman of Novas Software, a San Jose company he founded in 1996, was singled out for his contributions to the overall advancement of the EDA industry as an entrepreneur and a technologist, including his work in the areas of design emulation, verification, and debugging.

"[Paul Huang]is the personification of what we know as an entrepreneur, meaning that he created the building blocks of technology and translated them into commercial successes that today populate our industry," said Ray Bingham, CEO of Cadence Design Systems. "I think it is safe to say that the design infrastructure industry would be very different-and far less advanced-without Paul's contributions."

Huang has been involved in the EDA industry since the early 1980's and is best known as the developer of the Dracula physical design verification system and principal founder of ECAD, which is today part of Cadence. First introduced into the market in 1983, Dracula is still sold by Cadence today.

As the principal founder of Pie Design Systems, which merged with Quickturn in 1993, Huang also built the engineering team that created the first timing-correct emulator. Most recently, Huang founded Novas Software, which provides an integrated design debugging system for analysis and verification of complex system-on-a-chip designs.

"If you consider each of these entrepreneurial activities-from layout verification, to system emulation at the gate level, to Novas' system-level debug at the RTL level-you soon see that Paul has been recognizing opportunities and moving up the EDA food chain for more than twenty years, " said Richard Newton, dean of the College of Engineering at UC-Berkeley.

Huang studied as an undergraduate student at National Chiao Tung University in Taiwan, where his research work was focused on circuit simulation. In 1975, Huang went to Santa Clara University and graduated with his Ph.D. His dissertation was focused on physical mask resizing to compensate for the effects of photolithographic systems and IC processing. After graduating from Santa Clara, Huang joined National Semiconductor in its memory division. In 1980, he began work at Gould Systems Engineering Laboratory.

"It is not only technical excellence, passion, and drive that has made Paul the successful entrepreneur that he is today," Newton said. "I can still hear Paul's words as he explained to me Polish, Innovate, and Enjoy-Pie. 'First you polish the software, then you innovate some more, but the most important thing is to enjoy what you are doing. Polish, innovate, and enjoy.' Paul, what a great philosophy for any engineer, but especially for an entrepreneur."

Following the death in 1992 of EDA veteran Phil Kaufman, an active member of the consortium, EDAC conceived and instituted this annual award to be given in his name, recognizing individuals who have significantly advanced the field of electronic design automation.

Previous recipients include Hugo De Man, Ernest S. Kuh, James E. Solomon, Carver A. Mead, Donald O. Pederson, and Hermann K. Gummel.

• Altera Corp. (San Jose, CA) announced the grand opening of the Toronto Technology Center. The Toronto Technology Center will operate in conjunction with Altera's worldwide R&D facilities to enable accelerated development of future software and device architectures for system-on-a-programmable-chip (SOPC) technologies. Research and development activities in this new facility will utilize the programmable logic knowledge and resources available from the University of Toronto's engineering program.

• Synopsys, Inc. (Mountain View, CA) and STMicroelectronics (Geneva) have formed a multi-phased technology alliance to develop and deploy advanced design-for-test (DFT) solutions for complex system-on-a-chip (SOC). STMicroelectronics will use its expertise in SOC design to identify new DFT requirements. Synopsys will expand and enhance its DFT solutions, which are already in use within STMicroelectronics. The initial focus of this alliance will be to improve ST's SOC DFT flows in order to more quickly and predictably achieve DFT closure. Synopsys will provide new and existing DFT tools for deployment and integration into ST's SOC test analysis, synthesis, pattern generation, and verification flows over the course of the next year. - In a move that will allow processor intellectual property (IP) providers to publish certified benchmark scores on processor designs before first silicon, EEMBC, the embedded processor benchmark consortium, announced that it has established a new method that will enable its members to obtain certified benchmarks on the basis of simulation techniques. Until now, the publication of EEMBC benchmark scores required that the tests be performed on production silicon. The new rules allow IP vendors to publish scores based on simulation, provided that a set of rules established by EEMBC are followed in the benchmarking process and that scores are identified as being based on simulation rather than on an actual chip. The new EEMBC regulations for simulation benchmarking require that the simulator accurately reflect real-world characteristics with cycle accuracy. Both hardware and software simulations are allowed. Vendors must provide a simulation of a processor system with all resources needed to run the timed portions of the benchmark suite, rather than just the processor core. According to the EEMBC regulations, publishers of simulation-based scores must also certify that they have verified the simulator against register transfer language. EEMBC's Certification Labs (ECL) will re-create the simulation environment, re-execute the benchmarks on that simulator, and verify the disclosure reports in the same manner as for hardware-based certification, but scores will be reported in cycles rather than time as is done with benchmarks run on production silicon. EEMBC standards specify over 40 different benchmarks, each representing a different workload and stressing a different processor capability. Benchmark suites are organized to test devices for performance in automotive/industrial, networking, consumer, and office automation applications. Tality Corp. (San Jose, CA), a subsidiary of Cadence, and Sirius Communications NV (Rotselaar, Belgium) announced that they would collaborate on turnkey development of third-generation (3G) mobile phone applications. Under their non-exclusive agreement, Tality will incorporate Sirius' wide-band CDMA baseband core into its 3G design service offering. The two companies aim to accelerate the design cycle for 3G wireless multimedia information devices, such as smart phones and Internet-enabled personal communicators. The Sirius CDMA baseband solution-dubbed CDMAx-is a low-power software-configurable intellectual property core for 3G wireless handsets. Tality also announced that Sirius has become a member of its Surelink supply-chain partner network. Surelink enables providers in the electronic system and IC supply chains to integrate their offerings with those of Tality. Silicon Perspective Corp. (SPC; Santa Clara, CA) signed an agreement with Novas Software, Inc. (San Jose, CA) to OEM Novas' Debussy nWave and nSchema products. SPC has integrated nSchema into its First Encounter full-chip front-end physical design environment and nWave into its new Power Designer engine in First Encounter. nSchema analyzes the design and generates debug-specific logic diagrams that help engineers understand complex or unfamiliar designs. nWave displays waveforms to show signal values over time. SPC's First Encounter software helps engineers understand and fix timing problems in multi-million gate designs at the top level, with the partitioning, pin assignment, and interconnect between the blocks.

• Cadence Design Systems, Inc. (San Jose, CA) appointed Glen S. Fukushima president of Cadence Japan, Ltd. In this role, Fukushima will lead the company's day-to-day operations as it continues to serve Japan's semiconductor and systems companies in the design of electronics products. He will report to Ray Bingham, president and CEO of Cadence. He succeeds Jim Hogan, who will continue to support Japanese Market Development from his new assignment at the company headquarters in San Jose. Prior to joining the company, Fukushima served for two and a half years as president and representative director of the Japan operations of Arthur D. Little, Inc. (ADL), the management consulting firm. From 1990 to 1998, he held senior management positions at AT&T Corp., including serving as vice president of AT&T Japan, Ltd. and serving on the board of directors of AT&T's Internet access company in Japan.

• ASIC Alliance Corp. (Woburn, MA) elected Samuel H. Fuller to its board of directors. Currently, Fuller is vice president of research and development at Analog Devices in Norwood, MA. He will provide ASIC Alliance board with a deeper understanding and unique perspective on high-tech research and development, the company said. Fuller joined Analog Devices as vice president of research and development in early 1998. At Analog Devices, Fuller leads work on technology strategy, design tools and methods, and university research programs. Prior to joining Analog Devices, he was vice president of research for Digital Equipment Corp., where he was responsible for establishing and leading Digital's worldwide research organization with laboratories in California, Massachusetts, and Europe. Prior to Digital, Fuller was an associate professor of computer science and electrical engineering at Carnegie-Mellon University.

• Kymata Ltd. (Livingston, Scotland), a designer and manufacturer of planar optical components and subsystems, appointed David Plekenpol as the company's vice president of global sales and marketing. In this position, he will oversee Kymata's worldwide sales, systems engineering, business development and product marketing. Plekenpol was with Lucent Technologies as vice president of product marketing for the Optical Networking Group, based in The Netherlands. There he managed the marketing and positioning for Lucent's billion dollar optical networking business in the Europe, Middle East, and Africa region. Prior to his tenure in The Netherlands, Plekenpol spent three years in Lucent's Hong Kong and Singapore offices working on penetrating the CDMA, GSM, and fixed wireless markets.

• Cadence Design Systems, Inc. (San Jose, CA) reported third quarter revenues of $332 million and $0.14 diluted earnings per share. In the third quarter, the company booked 45 percent of its software products under the subscription model, exceeding its goal of 30 percent. For comparative purposes, except where noted, the results released reflect earnings before unusual items and amortization of acquired intangibles. The $332 million in third-quarter revenue represents a 47 percent increase over the comparable quarter in 1999. Product revenue for the third quarter of 2000 totaled $165 million, a 105 percent increase over the third quarter of last year and an 18 percent increase over last quarter. Total services revenue was $87 million, a 19 percent increase over the third quarter of 1999, with overall gross margin improving to 36 percent. Tality Corp., the company's design services business, contributed $52 million of this services revenue.
• Innoveda, Inc. (Marlboro, MA) announced financial results for the third quarter ended September 30, 2000. Formed by the March 2000 merger of Viewlogic Systems, Inc. and Summit Design, Inc., Innoveda reported revenue of $23.1 million, an increase of 70 percent over revenue of $13.6 million reported for the comparable 1999 quarter. Since Viewlogic was the acquirer for accounting purposes in the above merger, reported results for prior periods must be for Viewlogic only. Third quarter and nine-month results include one week of operations for PADS Software, Inc., which was acquired September 22, 2000. On the same basis, operating income before amortization and one-time charges for the quarter increased to $3.3 million from $1.1 million in the 1999 third quarter. Earnings per share, excluding amortization and non-recurring charges, increased to $0.06 from $0.02 for the quarter. Including amortization and merger-related charges, the company reported a net loss of $4.8 million, or $0.14 per share, for the third quarter of 2000. Revenue for the nine months ended September 30, 2000 increased to $59.0 million from $40.8 million for the comparable year-to-date 1999 period. Including amortization and merger-related charges, the company reported a net loss of $9.9 million, or $0.40 per share, for the nine months ended September 30, 2000. In other company news, its board of directors has authorized the repurchase of up to 2,000,000 shares of Innoveda's common stock. Innoveda had approximately 39,300,000 shares outstanding as of September 30, 2000. - Sapphire Design Automation (Santa Clara, CA) reported that it achieved record revenues in the 3rd quarter this year. Revenues were three times greater than in the same quarter last year, the company said.

• Sapphire also announced that it now has 15 accounts. Sapphire's new customers include MMC Networks (Sunnyvale, CA), Controlnet (San Jose, CA), Silicon Access Networks (San Jose CA), Kawasaki LSI (Japan), and MorphICs (Campbell, CA). Repeat business came from customers such as Procket Networks (San Jose, CA) and Sibyte (Santa Clara, CA) in Q3.

• Numetrics Management Systems (Santa Clara, CA), a provider of Internet-based engineering management software, announced that it received $1.2 million in financing from a group of angel investors. The funds will further the development of the company's Internet-based engineering management software tools. Numetrics recently unveiled its first Internet-based offering, the Design Productivity Management System (DPMS), which measures the design productivity of chip design teams. Among the Numetrics investors is Glen Antle, co-founder of Cadence Design Systems. Virtual Silicon Technology, Inc. (Sunnyvale, CA) has accepted over $15 million in a second round of funding from several high technology venture capital firms. Jointly leading the Series B equity round are Information Technology Ventures of Palo Alto, CA, and Walden International Investment Group of San Francisco, CA. The company will use these new funds to drive new product development, enhance its design automation infrastructure, and expand the company's customer support organization and new web-based delivery system. The company is a supplier of embedded semiconductor technology to manufacturers and designers of complex system-on-a-chip. The company provides process-specific embedded components including standard cell libraries, I/Os, SRAM compilers, mixed-signal functions, PLL compilers and embedded flash/EEPROM solutions.